2016-11-30 01:51:19 +00:00
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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2016-10-07 00:16:09 +01:00
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#include "radv_meta.h"
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#include "nir/nir_builder.h"
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2016-11-30 01:51:19 +00:00
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/*
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2016-11-30 03:10:28 +00:00
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* GFX queue: Compute shader implementation of image->buffer copy
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* Compute queue: implementation also of buffer->image, image->image, and image clear.
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2016-11-30 01:51:19 +00:00
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*/
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2017-12-19 03:55:18 +00:00
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/* GFX9 needs to use a 3D sampler to access 3D resources, so the shader has the options
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* for that.
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*/
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2016-10-07 00:16:09 +01:00
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static nir_shader *
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2017-12-19 03:55:18 +00:00
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build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
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2016-10-07 00:16:09 +01:00
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{
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nir_builder b;
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2017-12-19 03:55:18 +00:00
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enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
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const struct glsl_type *sampler_type = glsl_sampler_type(dim,
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2016-10-07 00:16:09 +01:00
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false,
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false,
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GLSL_TYPE_FLOAT);
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const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF,
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false,
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false,
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GLSL_TYPE_FLOAT);
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
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2017-12-19 03:55:18 +00:00
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b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
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2017-05-08 17:20:21 +01:00
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b.shader->info.cs.local_size[0] = 16;
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b.shader->info.cs.local_size[1] = 16;
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b.shader->info.cs.local_size[2] = 1;
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2016-10-07 00:16:09 +01:00
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
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sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
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img_type, "out_img");
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
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nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
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nir_ssa_def *block_size = nir_imm_ivec4(&b,
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2017-05-08 17:20:21 +01:00
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b.shader->info.cs.local_size[0],
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b.shader->info.cs.local_size[1],
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b.shader->info.cs.local_size[2], 0);
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2016-10-07 00:16:09 +01:00
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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2017-05-05 01:42:40 +01:00
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nir_intrinsic_set_base(offset, 0);
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2017-12-19 03:55:18 +00:00
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nir_intrinsic_set_range(offset, 16);
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2016-10-07 00:16:09 +01:00
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offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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2017-12-19 03:55:18 +00:00
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offset->num_components = is_3d ? 3 : 2;
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nir_ssa_dest_init(&offset->instr, &offset->dest, is_3d ? 3 : 2, 32, "offset");
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2016-10-07 00:16:09 +01:00
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nir_builder_instr_insert(&b, &offset->instr);
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nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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2017-05-05 01:42:40 +01:00
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nir_intrinsic_set_base(stride, 0);
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2017-12-19 03:55:18 +00:00
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nir_intrinsic_set_range(stride, 16);
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stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
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2016-10-07 00:16:09 +01:00
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stride->num_components = 1;
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nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
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nir_builder_instr_insert(&b, &stride->instr);
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nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa);
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
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2017-12-19 03:55:18 +00:00
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tex->sampler_dim = dim;
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2016-10-07 00:16:09 +01:00
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tex->op = nir_texop_txf;
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tex->src[0].src_type = nir_tex_src_coord;
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2017-12-19 03:55:18 +00:00
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tex->src[0].src = nir_src_for_ssa(nir_channels(&b, img_coord, is_3d ? 0x7 : 0x3));
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2016-10-07 00:16:09 +01:00
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tex->src[1].src_type = nir_tex_src_lod;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->dest_type = nir_type_float;
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tex->is_array = false;
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2017-12-19 03:55:18 +00:00
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tex->coord_components = is_3d ? 3 : 2;
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2016-10-07 00:16:09 +01:00
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tex->texture = nir_deref_var_create(tex, input_img);
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tex->sampler = NULL;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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nir_ssa_def *pos_x = nir_channel(&b, global_id, 0);
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nir_ssa_def *pos_y = nir_channel(&b, global_id, 1);
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nir_ssa_def *tmp = nir_imul(&b, pos_y, &stride->dest.ssa);
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tmp = nir_iadd(&b, tmp, pos_x);
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nir_ssa_def *coord = nir_vec4(&b, tmp, tmp, tmp, tmp);
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nir_ssa_def *outval = &tex->dest.ssa;
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
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store->src[0] = nir_src_for_ssa(coord);
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store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
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store->src[2] = nir_src_for_ssa(outval);
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store->variables[0] = nir_deref_var_create(store, output_img);
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nir_builder_instr_insert(&b, &store->instr);
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return b.shader;
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}
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/* Image to buffer - don't write use image accessors */
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static VkResult
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radv_device_init_meta_itob_state(struct radv_device *device)
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{
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VkResult result;
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struct radv_shader_module cs = { .nir = NULL };
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2017-12-19 03:55:18 +00:00
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struct radv_shader_module cs_3d = { .nir = NULL };
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2016-10-07 00:16:09 +01:00
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2017-12-19 03:55:18 +00:00
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cs.nir = build_nir_itob_compute_shader(device, false);
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if (device->physical_device->rad_info.chip_class >= GFX9)
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cs_3d.nir = build_nir_itob_compute_shader(device, true);
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2016-10-07 00:16:09 +01:00
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/*
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* two descriptors one for the image being sampled
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* one for the buffer being written.
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*/
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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2017-04-13 23:26:59 +01:00
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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2016-10-07 00:16:09 +01:00
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]) {
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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}
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};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
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&ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.itob.img_ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.itob.img_ds_layout,
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.pushConstantRangeCount = 1,
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2017-12-19 03:55:18 +00:00
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
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2016-10-07 00:16:09 +01:00
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device),
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&pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.itob.img_p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = radv_shader_module_to_handle(&cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.itob.img_p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, &vk_pipeline_info, NULL,
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&device->meta_state.itob.pipeline);
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if (result != VK_SUCCESS)
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goto fail;
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2017-12-19 03:55:18 +00:00
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = radv_shader_module_to_handle(&cs_3d),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info_3d = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage_3d,
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.flags = 0,
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.layout = device->meta_state.itob.img_p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, &vk_pipeline_info_3d, NULL,
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&device->meta_state.itob.pipeline_3d);
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if (result != VK_SUCCESS)
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goto fail;
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ralloc_free(cs_3d.nir);
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}
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2016-10-07 00:16:09 +01:00
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ralloc_free(cs.nir);
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2017-12-19 03:55:18 +00:00
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2016-10-07 00:16:09 +01:00
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return VK_SUCCESS;
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fail:
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ralloc_free(cs.nir);
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2017-12-19 03:55:18 +00:00
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ralloc_free(cs_3d.nir);
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2016-10-07 00:16:09 +01:00
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return result;
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}
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static void
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radv_device_finish_meta_itob_state(struct radv_device *device)
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{
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2017-09-28 12:50:56 +01:00
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struct radv_meta_state *state = &device->meta_state;
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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state->itob.img_p_layout, &state->alloc);
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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state->itob.img_ds_layout,
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&state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->itob.pipeline, &state->alloc);
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2017-12-19 03:55:18 +00:00
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if (device->physical_device->rad_info.chip_class >= GFX9)
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->itob.pipeline_3d, &state->alloc);
|
2016-10-07 00:16:09 +01:00
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}
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|
2016-11-29 23:52:55 +00:00
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static nir_shader *
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2017-12-28 23:20:21 +00:00
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build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
|
2016-11-29 23:52:55 +00:00
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{
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nir_builder b;
|
2017-12-28 23:20:21 +00:00
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enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
|
2016-11-29 23:52:55 +00:00
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const struct glsl_type *buf_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF,
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false,
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false,
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GLSL_TYPE_FLOAT);
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2017-12-28 23:20:21 +00:00
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const struct glsl_type *img_type = glsl_sampler_type(dim,
|
2016-11-29 23:52:55 +00:00
|
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false,
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false,
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GLSL_TYPE_FLOAT);
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
|
2017-12-28 23:20:21 +00:00
|
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b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
|
2017-05-08 17:20:21 +01:00
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b.shader->info.cs.local_size[0] = 16;
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|
|
|
b.shader->info.cs.local_size[1] = 16;
|
|
|
|
b.shader->info.cs.local_size[2] = 1;
|
2016-11-29 23:52:55 +00:00
|
|
|
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
|
|
|
|
buf_type, "s_tex");
|
|
|
|
input_img->data.descriptor_set = 0;
|
|
|
|
input_img->data.binding = 0;
|
|
|
|
|
|
|
|
nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
|
|
|
|
img_type, "out_img");
|
|
|
|
output_img->data.descriptor_set = 0;
|
|
|
|
output_img->data.binding = 1;
|
|
|
|
|
|
|
|
nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
|
|
|
|
nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
|
|
|
|
nir_ssa_def *block_size = nir_imm_ivec4(&b,
|
2017-05-08 17:20:21 +01:00
|
|
|
b.shader->info.cs.local_size[0],
|
|
|
|
b.shader->info.cs.local_size[1],
|
|
|
|
b.shader->info.cs.local_size[2], 0);
|
2016-11-29 23:52:55 +00:00
|
|
|
|
|
|
|
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
|
|
|
|
|
|
|
|
nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
|
2017-05-05 01:42:40 +01:00
|
|
|
nir_intrinsic_set_base(offset, 0);
|
2017-12-28 23:20:21 +00:00
|
|
|
nir_intrinsic_set_range(offset, 16);
|
2016-11-29 23:52:55 +00:00
|
|
|
offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
|
2017-12-28 23:20:21 +00:00
|
|
|
offset->num_components = is_3d ? 3 : 2;
|
|
|
|
nir_ssa_dest_init(&offset->instr, &offset->dest, is_3d ? 3 : 2, 32, "offset");
|
2016-11-29 23:52:55 +00:00
|
|
|
nir_builder_instr_insert(&b, &offset->instr);
|
|
|
|
|
|
|
|
nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
|
2017-05-05 01:42:40 +01:00
|
|
|
nir_intrinsic_set_base(stride, 0);
|
2017-12-28 23:20:21 +00:00
|
|
|
nir_intrinsic_set_range(stride, 16);
|
|
|
|
stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
|
2016-11-29 23:52:55 +00:00
|
|
|
stride->num_components = 1;
|
|
|
|
nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
|
|
|
|
nir_builder_instr_insert(&b, &stride->instr);
|
|
|
|
|
|
|
|
nir_ssa_def *pos_x = nir_channel(&b, global_id, 0);
|
|
|
|
nir_ssa_def *pos_y = nir_channel(&b, global_id, 1);
|
|
|
|
|
|
|
|
nir_ssa_def *tmp = nir_imul(&b, pos_y, &stride->dest.ssa);
|
|
|
|
tmp = nir_iadd(&b, tmp, pos_x);
|
|
|
|
|
|
|
|
nir_ssa_def *buf_coord = nir_vec4(&b, tmp, tmp, tmp, tmp);
|
|
|
|
|
|
|
|
nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa);
|
|
|
|
|
|
|
|
nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
|
|
|
|
tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
|
|
|
|
tex->op = nir_texop_txf;
|
|
|
|
tex->src[0].src_type = nir_tex_src_coord;
|
2017-03-08 22:26:13 +00:00
|
|
|
tex->src[0].src = nir_src_for_ssa(nir_channels(&b, buf_coord, 1));
|
2016-11-29 23:52:55 +00:00
|
|
|
tex->src[1].src_type = nir_tex_src_lod;
|
|
|
|
tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
|
|
|
|
tex->dest_type = nir_type_float;
|
|
|
|
tex->is_array = false;
|
|
|
|
tex->coord_components = 1;
|
|
|
|
tex->texture = nir_deref_var_create(tex, input_img);
|
|
|
|
tex->sampler = NULL;
|
|
|
|
|
|
|
|
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
|
|
|
|
nir_builder_instr_insert(&b, &tex->instr);
|
|
|
|
|
|
|
|
nir_ssa_def *outval = &tex->dest.ssa;
|
|
|
|
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
|
|
|
|
store->src[0] = nir_src_for_ssa(img_coord);
|
|
|
|
store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
|
|
|
|
store->src[2] = nir_src_for_ssa(outval);
|
|
|
|
store->variables[0] = nir_deref_var_create(store, output_img);
|
|
|
|
|
|
|
|
nir_builder_instr_insert(&b, &store->instr);
|
|
|
|
return b.shader;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Buffer to image - don't write use image accessors */
|
|
|
|
static VkResult
|
|
|
|
radv_device_init_meta_btoi_state(struct radv_device *device)
|
|
|
|
{
|
|
|
|
VkResult result;
|
|
|
|
struct radv_shader_module cs = { .nir = NULL };
|
2017-12-28 23:20:21 +00:00
|
|
|
struct radv_shader_module cs_3d = { .nir = NULL };
|
|
|
|
cs.nir = build_nir_btoi_compute_shader(device, false);
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9)
|
|
|
|
cs_3d.nir = build_nir_btoi_compute_shader(device, true);
|
2016-11-29 23:52:55 +00:00
|
|
|
/*
|
|
|
|
* two descriptors one for the image being sampled
|
|
|
|
* one for the buffer being written.
|
|
|
|
*/
|
|
|
|
VkDescriptorSetLayoutCreateInfo ds_create_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
|
2017-04-13 23:26:59 +01:00
|
|
|
.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
|
2016-11-29 23:52:55 +00:00
|
|
|
.bindingCount = 2,
|
|
|
|
.pBindings = (VkDescriptorSetLayoutBinding[]) {
|
|
|
|
{
|
|
|
|
.binding = 0,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.pImmutableSamplers = NULL
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.binding = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.pImmutableSamplers = NULL
|
|
|
|
},
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
|
|
|
|
&ds_create_info,
|
|
|
|
&device->meta_state.alloc,
|
|
|
|
&device->meta_state.btoi.img_ds_layout);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
|
|
|
|
VkPipelineLayoutCreateInfo pl_create_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
|
|
|
|
.setLayoutCount = 1,
|
|
|
|
.pSetLayouts = &device->meta_state.btoi.img_ds_layout,
|
|
|
|
.pushConstantRangeCount = 1,
|
2017-12-28 23:20:21 +00:00
|
|
|
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
|
2016-11-29 23:52:55 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreatePipelineLayout(radv_device_to_handle(device),
|
|
|
|
&pl_create_info,
|
|
|
|
&device->meta_state.alloc,
|
|
|
|
&device->meta_state.btoi.img_p_layout);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
/* compute shader */
|
|
|
|
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = radv_shader_module_to_handle(&cs),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.btoi.img_p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
|
|
|
1, &vk_pipeline_info, NULL,
|
|
|
|
&device->meta_state.btoi.pipeline);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
2017-12-28 23:20:21 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = radv_shader_module_to_handle(&cs_3d),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info_3d = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage_3d,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.btoi.img_p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
|
|
|
1, &vk_pipeline_info_3d, NULL,
|
|
|
|
&device->meta_state.btoi.pipeline_3d);
|
|
|
|
ralloc_free(cs_3d.nir);
|
|
|
|
}
|
2016-11-29 23:52:55 +00:00
|
|
|
ralloc_free(cs.nir);
|
2017-12-28 23:20:21 +00:00
|
|
|
|
2016-11-29 23:52:55 +00:00
|
|
|
return VK_SUCCESS;
|
|
|
|
fail:
|
2017-12-28 23:20:21 +00:00
|
|
|
ralloc_free(cs_3d.nir);
|
2016-11-29 23:52:55 +00:00
|
|
|
ralloc_free(cs.nir);
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_device_finish_meta_btoi_state(struct radv_device *device)
|
|
|
|
{
|
2017-09-28 12:50:56 +01:00
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
|
|
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
|
|
|
state->btoi.img_p_layout, &state->alloc);
|
|
|
|
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
|
|
|
state->btoi.img_ds_layout,
|
|
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->btoi.pipeline, &state->alloc);
|
2017-12-28 23:20:21 +00:00
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->btoi.pipeline_3d, &state->alloc);
|
2016-11-29 23:52:55 +00:00
|
|
|
}
|
|
|
|
|
2016-11-30 00:26:47 +00:00
|
|
|
static nir_shader *
|
2017-12-28 07:10:35 +00:00
|
|
|
build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
|
2016-11-30 00:26:47 +00:00
|
|
|
{
|
|
|
|
nir_builder b;
|
2017-12-28 07:10:35 +00:00
|
|
|
enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
|
|
|
|
const struct glsl_type *buf_type = glsl_sampler_type(dim,
|
2016-11-30 00:26:47 +00:00
|
|
|
false,
|
|
|
|
false,
|
|
|
|
GLSL_TYPE_FLOAT);
|
2017-12-28 07:10:35 +00:00
|
|
|
const struct glsl_type *img_type = glsl_sampler_type(dim,
|
2016-11-30 00:26:47 +00:00
|
|
|
false,
|
|
|
|
false,
|
|
|
|
GLSL_TYPE_FLOAT);
|
|
|
|
nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
|
2017-12-28 07:10:35 +00:00
|
|
|
b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_itoi_cs_3d" : "meta_itoi_cs");
|
2017-05-08 17:20:21 +01:00
|
|
|
b.shader->info.cs.local_size[0] = 16;
|
|
|
|
b.shader->info.cs.local_size[1] = 16;
|
|
|
|
b.shader->info.cs.local_size[2] = 1;
|
2016-11-30 00:26:47 +00:00
|
|
|
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
|
|
|
|
buf_type, "s_tex");
|
|
|
|
input_img->data.descriptor_set = 0;
|
|
|
|
input_img->data.binding = 0;
|
|
|
|
|
|
|
|
nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
|
|
|
|
img_type, "out_img");
|
|
|
|
output_img->data.descriptor_set = 0;
|
|
|
|
output_img->data.binding = 1;
|
|
|
|
|
|
|
|
nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
|
|
|
|
nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
|
|
|
|
nir_ssa_def *block_size = nir_imm_ivec4(&b,
|
2017-05-08 17:20:21 +01:00
|
|
|
b.shader->info.cs.local_size[0],
|
|
|
|
b.shader->info.cs.local_size[1],
|
|
|
|
b.shader->info.cs.local_size[2], 0);
|
2016-11-30 00:26:47 +00:00
|
|
|
|
|
|
|
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
|
|
|
|
|
|
|
|
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
|
2017-05-05 01:42:40 +01:00
|
|
|
nir_intrinsic_set_base(src_offset, 0);
|
2017-12-28 07:10:35 +00:00
|
|
|
nir_intrinsic_set_range(src_offset, 24);
|
2016-11-30 00:26:47 +00:00
|
|
|
src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
|
2017-12-28 07:10:35 +00:00
|
|
|
src_offset->num_components = is_3d ? 3 : 2;
|
|
|
|
nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, is_3d ? 3 : 2, 32, "src_offset");
|
2016-11-30 00:26:47 +00:00
|
|
|
nir_builder_instr_insert(&b, &src_offset->instr);
|
|
|
|
|
|
|
|
nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
|
2017-05-05 01:42:40 +01:00
|
|
|
nir_intrinsic_set_base(dst_offset, 0);
|
2017-12-28 07:10:35 +00:00
|
|
|
nir_intrinsic_set_range(dst_offset, 24);
|
|
|
|
dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
|
|
|
|
dst_offset->num_components = is_3d ? 3 : 2;
|
|
|
|
nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, is_3d ? 3 : 2, 32, "dst_offset");
|
2016-11-30 00:26:47 +00:00
|
|
|
nir_builder_instr_insert(&b, &dst_offset->instr);
|
|
|
|
|
|
|
|
nir_ssa_def *src_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa);
|
|
|
|
|
|
|
|
nir_ssa_def *dst_coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
|
|
|
|
|
|
|
|
nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
|
2017-12-28 07:10:35 +00:00
|
|
|
tex->sampler_dim = dim;
|
2016-11-30 00:26:47 +00:00
|
|
|
tex->op = nir_texop_txf;
|
|
|
|
tex->src[0].src_type = nir_tex_src_coord;
|
2017-12-28 07:10:35 +00:00
|
|
|
tex->src[0].src = nir_src_for_ssa(nir_channels(&b, src_coord, is_3d ? 0x7 : 0x3));
|
2016-11-30 00:26:47 +00:00
|
|
|
tex->src[1].src_type = nir_tex_src_lod;
|
|
|
|
tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
|
|
|
|
tex->dest_type = nir_type_float;
|
|
|
|
tex->is_array = false;
|
2017-12-28 07:10:35 +00:00
|
|
|
tex->coord_components = is_3d ? 3 : 2;
|
2016-11-30 00:26:47 +00:00
|
|
|
tex->texture = nir_deref_var_create(tex, input_img);
|
|
|
|
tex->sampler = NULL;
|
|
|
|
|
|
|
|
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
|
|
|
|
nir_builder_instr_insert(&b, &tex->instr);
|
|
|
|
|
|
|
|
nir_ssa_def *outval = &tex->dest.ssa;
|
|
|
|
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
|
|
|
|
store->src[0] = nir_src_for_ssa(dst_coord);
|
|
|
|
store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
|
|
|
|
store->src[2] = nir_src_for_ssa(outval);
|
|
|
|
store->variables[0] = nir_deref_var_create(store, output_img);
|
|
|
|
|
|
|
|
nir_builder_instr_insert(&b, &store->instr);
|
|
|
|
return b.shader;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* image to image - don't write use image accessors */
|
|
|
|
static VkResult
|
|
|
|
radv_device_init_meta_itoi_state(struct radv_device *device)
|
|
|
|
{
|
|
|
|
VkResult result;
|
|
|
|
struct radv_shader_module cs = { .nir = NULL };
|
2017-12-28 07:10:35 +00:00
|
|
|
struct radv_shader_module cs_3d = { .nir = NULL };
|
|
|
|
cs.nir = build_nir_itoi_compute_shader(device, false);
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9)
|
|
|
|
cs_3d.nir = build_nir_itoi_compute_shader(device, true);
|
2016-11-30 00:26:47 +00:00
|
|
|
/*
|
|
|
|
* two descriptors one for the image being sampled
|
|
|
|
* one for the buffer being written.
|
|
|
|
*/
|
|
|
|
VkDescriptorSetLayoutCreateInfo ds_create_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
|
2017-04-13 23:26:59 +01:00
|
|
|
.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
|
2016-11-30 00:26:47 +00:00
|
|
|
.bindingCount = 2,
|
|
|
|
.pBindings = (VkDescriptorSetLayoutBinding[]) {
|
|
|
|
{
|
|
|
|
.binding = 0,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.pImmutableSamplers = NULL
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.binding = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.pImmutableSamplers = NULL
|
|
|
|
},
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
|
|
|
|
&ds_create_info,
|
|
|
|
&device->meta_state.alloc,
|
|
|
|
&device->meta_state.itoi.img_ds_layout);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
|
|
|
|
VkPipelineLayoutCreateInfo pl_create_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
|
|
|
|
.setLayoutCount = 1,
|
|
|
|
.pSetLayouts = &device->meta_state.itoi.img_ds_layout,
|
|
|
|
.pushConstantRangeCount = 1,
|
2017-12-28 07:10:35 +00:00
|
|
|
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 24},
|
2016-11-30 00:26:47 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreatePipelineLayout(radv_device_to_handle(device),
|
|
|
|
&pl_create_info,
|
|
|
|
&device->meta_state.alloc,
|
|
|
|
&device->meta_state.itoi.img_p_layout);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
/* compute shader */
|
|
|
|
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = radv_shader_module_to_handle(&cs),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.itoi.img_p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
|
|
|
1, &vk_pipeline_info, NULL,
|
|
|
|
&device->meta_state.itoi.pipeline);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
2017-12-28 07:10:35 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = radv_shader_module_to_handle(&cs_3d),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info_3d = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage_3d,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.itoi.img_p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
|
|
|
1, &vk_pipeline_info_3d, NULL,
|
|
|
|
&device->meta_state.itoi.pipeline_3d);
|
|
|
|
|
|
|
|
ralloc_free(cs_3d.nir);
|
|
|
|
}
|
2016-11-30 00:26:47 +00:00
|
|
|
ralloc_free(cs.nir);
|
2017-12-28 07:10:35 +00:00
|
|
|
|
2016-11-30 00:26:47 +00:00
|
|
|
return VK_SUCCESS;
|
|
|
|
fail:
|
|
|
|
ralloc_free(cs.nir);
|
2017-12-28 07:10:35 +00:00
|
|
|
ralloc_free(cs_3d.nir);
|
2016-11-30 00:26:47 +00:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_device_finish_meta_itoi_state(struct radv_device *device)
|
|
|
|
{
|
2017-09-28 12:50:56 +01:00
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
|
|
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
|
|
|
state->itoi.img_p_layout, &state->alloc);
|
|
|
|
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
|
|
|
state->itoi.img_ds_layout,
|
|
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->itoi.pipeline, &state->alloc);
|
2017-12-28 07:10:35 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9)
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->itoi.pipeline_3d, &state->alloc);
|
2016-11-30 00:26:47 +00:00
|
|
|
}
|
|
|
|
|
2016-11-30 01:45:24 +00:00
|
|
|
static nir_shader *
|
2017-12-28 22:52:07 +00:00
|
|
|
build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
|
2016-11-30 01:45:24 +00:00
|
|
|
{
|
|
|
|
nir_builder b;
|
2017-12-28 22:52:07 +00:00
|
|
|
enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
|
|
|
|
const struct glsl_type *img_type = glsl_sampler_type(dim,
|
2016-11-30 01:45:24 +00:00
|
|
|
false,
|
|
|
|
false,
|
|
|
|
GLSL_TYPE_FLOAT);
|
|
|
|
nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
|
2017-12-28 22:52:07 +00:00
|
|
|
b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_cleari_cs_3d" : "meta_cleari_cs");
|
2017-05-08 17:20:21 +01:00
|
|
|
b.shader->info.cs.local_size[0] = 16;
|
|
|
|
b.shader->info.cs.local_size[1] = 16;
|
|
|
|
b.shader->info.cs.local_size[2] = 1;
|
2016-11-30 01:45:24 +00:00
|
|
|
|
|
|
|
nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
|
|
|
|
img_type, "out_img");
|
|
|
|
output_img->data.descriptor_set = 0;
|
|
|
|
output_img->data.binding = 0;
|
|
|
|
|
|
|
|
nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
|
|
|
|
nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
|
|
|
|
nir_ssa_def *block_size = nir_imm_ivec4(&b,
|
2017-05-08 17:20:21 +01:00
|
|
|
b.shader->info.cs.local_size[0],
|
|
|
|
b.shader->info.cs.local_size[1],
|
|
|
|
b.shader->info.cs.local_size[2], 0);
|
2016-11-30 01:45:24 +00:00
|
|
|
|
|
|
|
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
|
|
|
|
|
|
|
|
nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
|
2017-05-05 01:42:40 +01:00
|
|
|
nir_intrinsic_set_base(clear_val, 0);
|
2017-12-28 22:52:07 +00:00
|
|
|
nir_intrinsic_set_range(clear_val, 20);
|
2016-11-30 01:45:24 +00:00
|
|
|
clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
|
|
|
|
clear_val->num_components = 4;
|
|
|
|
nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 4, 32, "clear_value");
|
|
|
|
nir_builder_instr_insert(&b, &clear_val->instr);
|
|
|
|
|
2017-12-28 22:52:07 +00:00
|
|
|
nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
|
|
|
|
nir_intrinsic_set_base(layer, 0);
|
|
|
|
nir_intrinsic_set_range(layer, 20);
|
|
|
|
layer->src[0] = nir_src_for_ssa(nir_imm_int(&b, 16));
|
|
|
|
layer->num_components = 1;
|
|
|
|
nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
|
|
|
|
nir_builder_instr_insert(&b, &layer->instr);
|
|
|
|
|
|
|
|
nir_ssa_def *global_z = nir_iadd(&b, nir_channel(&b, global_id, 2), &layer->dest.ssa);
|
|
|
|
|
|
|
|
nir_ssa_def *comps[4];
|
|
|
|
comps[0] = nir_channel(&b, global_id, 0);
|
|
|
|
comps[1] = nir_channel(&b, global_id, 1);
|
|
|
|
comps[2] = global_z;
|
|
|
|
comps[3] = nir_imm_int(&b, 0);
|
|
|
|
global_id = nir_vec(&b, comps, 4);
|
|
|
|
|
2016-11-30 01:45:24 +00:00
|
|
|
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
|
|
|
|
store->src[0] = nir_src_for_ssa(global_id);
|
|
|
|
store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
|
|
|
|
store->src[2] = nir_src_for_ssa(&clear_val->dest.ssa);
|
|
|
|
store->variables[0] = nir_deref_var_create(store, output_img);
|
|
|
|
|
|
|
|
nir_builder_instr_insert(&b, &store->instr);
|
|
|
|
return b.shader;
|
|
|
|
}
|
|
|
|
|
|
|
|
static VkResult
|
|
|
|
radv_device_init_meta_cleari_state(struct radv_device *device)
|
|
|
|
{
|
|
|
|
VkResult result;
|
|
|
|
struct radv_shader_module cs = { .nir = NULL };
|
2017-12-28 22:52:07 +00:00
|
|
|
struct radv_shader_module cs_3d = { .nir = NULL };
|
|
|
|
cs.nir = build_nir_cleari_compute_shader(device, false);
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9)
|
|
|
|
cs_3d.nir = build_nir_cleari_compute_shader(device, true);
|
2016-11-30 01:45:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* two descriptors one for the image being sampled
|
|
|
|
* one for the buffer being written.
|
|
|
|
*/
|
|
|
|
VkDescriptorSetLayoutCreateInfo ds_create_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
|
2017-04-13 23:26:59 +01:00
|
|
|
.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
|
2016-11-30 01:45:24 +00:00
|
|
|
.bindingCount = 1,
|
|
|
|
.pBindings = (VkDescriptorSetLayoutBinding[]) {
|
|
|
|
{
|
|
|
|
.binding = 0,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.pImmutableSamplers = NULL
|
|
|
|
},
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
|
|
|
|
&ds_create_info,
|
|
|
|
&device->meta_state.alloc,
|
|
|
|
&device->meta_state.cleari.img_ds_layout);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
|
|
|
|
VkPipelineLayoutCreateInfo pl_create_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
|
|
|
|
.setLayoutCount = 1,
|
|
|
|
.pSetLayouts = &device->meta_state.cleari.img_ds_layout,
|
|
|
|
.pushConstantRangeCount = 1,
|
2017-12-28 22:52:07 +00:00
|
|
|
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 20},
|
2016-11-30 01:45:24 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreatePipelineLayout(radv_device_to_handle(device),
|
|
|
|
&pl_create_info,
|
|
|
|
&device->meta_state.alloc,
|
|
|
|
&device->meta_state.cleari.img_p_layout);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
/* compute shader */
|
|
|
|
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = radv_shader_module_to_handle(&cs),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.cleari.img_p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
|
|
|
1, &vk_pipeline_info, NULL,
|
|
|
|
&device->meta_state.cleari.pipeline);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
2017-12-28 22:52:07 +00:00
|
|
|
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
/* compute shader */
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = radv_shader_module_to_handle(&cs_3d),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info_3d = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage_3d,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.cleari.img_p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
|
|
|
1, &vk_pipeline_info_3d, NULL,
|
|
|
|
&device->meta_state.cleari.pipeline_3d);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
ralloc_free(cs_3d.nir);
|
|
|
|
}
|
2016-11-30 01:45:24 +00:00
|
|
|
ralloc_free(cs.nir);
|
|
|
|
return VK_SUCCESS;
|
|
|
|
fail:
|
|
|
|
ralloc_free(cs.nir);
|
2017-12-28 22:52:07 +00:00
|
|
|
ralloc_free(cs_3d.nir);
|
2016-11-30 01:45:24 +00:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_device_finish_meta_cleari_state(struct radv_device *device)
|
|
|
|
{
|
2017-09-28 12:50:56 +01:00
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
|
|
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
|
|
|
state->cleari.img_p_layout, &state->alloc);
|
|
|
|
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
|
|
|
state->cleari.img_ds_layout,
|
|
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->cleari.pipeline, &state->alloc);
|
2017-12-28 22:52:07 +00:00
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->cleari.pipeline_3d, &state->alloc);
|
2016-11-30 01:45:24 +00:00
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
void
|
|
|
|
radv_device_finish_meta_bufimage_state(struct radv_device *device)
|
|
|
|
{
|
|
|
|
radv_device_finish_meta_itob_state(device);
|
2016-11-29 23:52:55 +00:00
|
|
|
radv_device_finish_meta_btoi_state(device);
|
2016-11-30 00:26:47 +00:00
|
|
|
radv_device_finish_meta_itoi_state(device);
|
2016-11-30 01:45:24 +00:00
|
|
|
radv_device_finish_meta_cleari_state(device);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_device_init_meta_bufimage_state(struct radv_device *device)
|
|
|
|
{
|
|
|
|
VkResult result;
|
|
|
|
|
|
|
|
result = radv_device_init_meta_itob_state(device);
|
|
|
|
if (result != VK_SUCCESS)
|
2018-01-21 21:01:49 +00:00
|
|
|
goto fail_itob;
|
2016-11-29 23:52:55 +00:00
|
|
|
|
|
|
|
result = radv_device_init_meta_btoi_state(device);
|
2016-11-30 01:45:24 +00:00
|
|
|
if (result != VK_SUCCESS)
|
2018-01-21 21:01:49 +00:00
|
|
|
goto fail_btoi;
|
2016-11-30 00:26:47 +00:00
|
|
|
|
|
|
|
result = radv_device_init_meta_itoi_state(device);
|
2016-11-30 01:45:24 +00:00
|
|
|
if (result != VK_SUCCESS)
|
2018-01-21 21:01:49 +00:00
|
|
|
goto fail_itoi;
|
2016-11-30 01:45:24 +00:00
|
|
|
|
|
|
|
result = radv_device_init_meta_cleari_state(device);
|
|
|
|
if (result != VK_SUCCESS)
|
2018-01-21 21:01:49 +00:00
|
|
|
goto fail_cleari;
|
2016-11-30 01:45:24 +00:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
return VK_SUCCESS;
|
2018-01-21 21:01:49 +00:00
|
|
|
fail_cleari:
|
|
|
|
radv_device_finish_meta_cleari_state(device);
|
2016-11-30 01:45:24 +00:00
|
|
|
fail_itoi:
|
|
|
|
radv_device_finish_meta_itoi_state(device);
|
|
|
|
fail_btoi:
|
|
|
|
radv_device_finish_meta_btoi_state(device);
|
|
|
|
fail_itob:
|
|
|
|
radv_device_finish_meta_itob_state(device);
|
|
|
|
return result;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
create_iview(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_meta_blit2d_surf *surf,
|
|
|
|
struct radv_image_view *iview)
|
|
|
|
{
|
2017-12-19 03:55:18 +00:00
|
|
|
VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D :
|
|
|
|
radv_meta_get_view_type(surf->image);
|
2016-10-07 00:16:09 +01:00
|
|
|
radv_image_view_init(iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo) {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(surf->image),
|
2017-12-19 03:55:18 +00:00
|
|
|
.viewType = view_type,
|
2016-10-07 00:16:09 +01:00
|
|
|
.format = surf->format,
|
|
|
|
.subresourceRange = {
|
|
|
|
.aspectMask = surf->aspect_mask,
|
|
|
|
.baseMipLevel = surf->level,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = surf->layer,
|
|
|
|
.layerCount = 1
|
|
|
|
},
|
2017-06-25 21:25:47 +01:00
|
|
|
});
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
create_bview(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_buffer *buffer,
|
|
|
|
unsigned offset,
|
|
|
|
VkFormat format,
|
|
|
|
struct radv_buffer_view *bview)
|
|
|
|
{
|
|
|
|
radv_buffer_view_init(bview, cmd_buffer->device,
|
|
|
|
&(VkBufferViewCreateInfo) {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
|
|
|
|
.flags = 0,
|
|
|
|
.buffer = radv_buffer_to_handle(buffer),
|
|
|
|
.format = format,
|
|
|
|
.offset = offset,
|
|
|
|
.range = VK_WHOLE_SIZE,
|
2017-09-12 18:08:45 +01:00
|
|
|
});
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
itob_bind_descriptors(struct radv_cmd_buffer *cmd_buffer,
|
2017-10-17 10:04:36 +01:00
|
|
|
struct radv_image_view *src,
|
|
|
|
struct radv_buffer_view *dst)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-04-13 23:26:59 +01:00
|
|
|
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer,
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
device->meta_state.itob.img_p_layout,
|
|
|
|
0, /* set */
|
|
|
|
2, /* descriptorWriteCount */
|
|
|
|
(VkWriteDescriptorSet[]) {
|
|
|
|
{
|
|
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 0,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]) {
|
|
|
|
{
|
|
|
|
.sampler = VK_NULL_HANDLE,
|
2017-10-17 10:04:36 +01:00
|
|
|
.imageView = radv_image_view_to_handle(src),
|
2017-04-13 23:26:59 +01:00
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 1,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
|
2017-10-17 10:04:36 +01:00
|
|
|
.pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(dst) },
|
2017-04-13 23:26:59 +01:00
|
|
|
}
|
|
|
|
});
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_meta_blit2d_surf *src,
|
|
|
|
struct radv_meta_blit2d_buffer *dst,
|
|
|
|
unsigned num_rects,
|
|
|
|
struct radv_meta_blit2d_rect *rects)
|
|
|
|
{
|
2017-10-04 21:27:39 +01:00
|
|
|
VkPipeline pipeline = cmd_buffer->device->meta_state.itob.pipeline;
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-10-17 10:04:36 +01:00
|
|
|
struct radv_image_view src_view;
|
|
|
|
struct radv_buffer_view dst_view;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-10-17 10:04:36 +01:00
|
|
|
create_iview(cmd_buffer, src, &src_view);
|
|
|
|
create_bview(cmd_buffer, dst->buffer, dst->offset, dst->format, &dst_view);
|
|
|
|
itob_bind_descriptors(cmd_buffer, &src_view, &dst_view);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-12-19 03:55:18 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
src->image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pipeline = cmd_buffer->device->meta_state.itob.pipeline_3d;
|
2017-10-04 21:27:39 +01:00
|
|
|
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2016-11-30 01:56:11 +00:00
|
|
|
for (unsigned r = 0; r < num_rects; ++r) {
|
2017-12-19 03:55:18 +00:00
|
|
|
unsigned push_constants[4] = {
|
2016-10-07 00:16:09 +01:00
|
|
|
rects[r].src_x,
|
|
|
|
rects[r].src_y,
|
2017-12-19 03:55:18 +00:00
|
|
|
src->layer,
|
2016-10-07 00:16:09 +01:00
|
|
|
dst->pitch
|
|
|
|
};
|
|
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
device->meta_state.itob.img_p_layout,
|
2017-12-19 03:55:18 +00:00
|
|
|
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
|
2016-10-07 00:16:09 +01:00
|
|
|
push_constants);
|
|
|
|
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
|
|
|
|
}
|
|
|
|
}
|
2016-11-29 23:52:55 +00:00
|
|
|
|
|
|
|
static void
|
|
|
|
btoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer,
|
2017-10-17 10:04:36 +01:00
|
|
|
struct radv_buffer_view *src,
|
|
|
|
struct radv_image_view *dst)
|
2016-11-29 23:52:55 +00:00
|
|
|
{
|
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-04-13 23:26:59 +01:00
|
|
|
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer,
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
device->meta_state.btoi.img_p_layout,
|
|
|
|
0, /* set */
|
|
|
|
2, /* descriptorWriteCount */
|
|
|
|
(VkWriteDescriptorSet[]) {
|
|
|
|
{
|
|
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 0,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
|
2017-10-17 10:04:36 +01:00
|
|
|
.pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(src) },
|
2017-04-13 23:26:59 +01:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 1,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]) {
|
|
|
|
{
|
|
|
|
.sampler = VK_NULL_HANDLE,
|
2017-10-17 10:04:36 +01:00
|
|
|
.imageView = radv_image_view_to_handle(dst),
|
2017-04-13 23:26:59 +01:00
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}
|
|
|
|
}
|
|
|
|
});
|
2016-11-29 23:52:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_meta_blit2d_buffer *src,
|
|
|
|
struct radv_meta_blit2d_surf *dst,
|
|
|
|
unsigned num_rects,
|
|
|
|
struct radv_meta_blit2d_rect *rects)
|
|
|
|
{
|
2017-10-04 21:27:39 +01:00
|
|
|
VkPipeline pipeline = cmd_buffer->device->meta_state.btoi.pipeline;
|
2016-11-29 23:52:55 +00:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-10-17 10:04:36 +01:00
|
|
|
struct radv_buffer_view src_view;
|
|
|
|
struct radv_image_view dst_view;
|
2016-11-29 23:52:55 +00:00
|
|
|
|
2017-10-17 10:04:36 +01:00
|
|
|
create_bview(cmd_buffer, src->buffer, src->offset, src->format, &src_view);
|
|
|
|
create_iview(cmd_buffer, dst, &dst_view);
|
|
|
|
btoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
|
2016-11-29 23:52:55 +00:00
|
|
|
|
2017-12-28 23:20:21 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
dst->image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pipeline = cmd_buffer->device->meta_state.btoi.pipeline_3d;
|
2017-10-04 21:27:39 +01:00
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
|
2016-11-29 23:52:55 +00:00
|
|
|
|
|
|
|
for (unsigned r = 0; r < num_rects; ++r) {
|
2017-12-28 23:20:21 +00:00
|
|
|
unsigned push_constants[4] = {
|
2016-11-29 23:52:55 +00:00
|
|
|
rects[r].dst_x,
|
|
|
|
rects[r].dst_y,
|
2017-12-28 23:20:21 +00:00
|
|
|
dst->layer,
|
|
|
|
src->pitch,
|
2016-11-29 23:52:55 +00:00
|
|
|
};
|
|
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
device->meta_state.btoi.img_p_layout,
|
2017-12-28 23:20:21 +00:00
|
|
|
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
|
2016-11-29 23:52:55 +00:00
|
|
|
push_constants);
|
|
|
|
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
|
|
|
|
}
|
|
|
|
}
|
2016-11-30 00:26:47 +00:00
|
|
|
|
|
|
|
static void
|
|
|
|
itoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer,
|
2017-10-17 10:04:36 +01:00
|
|
|
struct radv_image_view *src,
|
|
|
|
struct radv_image_view *dst)
|
2016-11-30 00:26:47 +00:00
|
|
|
{
|
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-04-13 23:26:59 +01:00
|
|
|
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer,
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
device->meta_state.itoi.img_p_layout,
|
|
|
|
0, /* set */
|
|
|
|
2, /* descriptorWriteCount */
|
|
|
|
(VkWriteDescriptorSet[]) {
|
|
|
|
{
|
|
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 0,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]) {
|
|
|
|
{
|
|
|
|
.sampler = VK_NULL_HANDLE,
|
2017-10-17 10:04:36 +01:00
|
|
|
.imageView = radv_image_view_to_handle(src),
|
2017-04-13 23:26:59 +01:00
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 1,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]) {
|
|
|
|
{
|
|
|
|
.sampler = VK_NULL_HANDLE,
|
2017-10-17 10:04:36 +01:00
|
|
|
.imageView = radv_image_view_to_handle(dst),
|
2017-04-13 23:26:59 +01:00
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}
|
|
|
|
}
|
|
|
|
});
|
2016-11-30 00:26:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_meta_blit2d_surf *src,
|
|
|
|
struct radv_meta_blit2d_surf *dst,
|
|
|
|
unsigned num_rects,
|
|
|
|
struct radv_meta_blit2d_rect *rects)
|
|
|
|
{
|
2017-10-04 21:27:39 +01:00
|
|
|
VkPipeline pipeline = cmd_buffer->device->meta_state.itoi.pipeline;
|
2016-11-30 00:26:47 +00:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-10-17 10:04:36 +01:00
|
|
|
struct radv_image_view src_view, dst_view;
|
2016-11-30 00:26:47 +00:00
|
|
|
|
2017-10-17 10:04:36 +01:00
|
|
|
create_iview(cmd_buffer, src, &src_view);
|
|
|
|
create_iview(cmd_buffer, dst, &dst_view);
|
2016-11-30 00:26:47 +00:00
|
|
|
|
2017-10-17 10:04:36 +01:00
|
|
|
itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
|
2016-11-30 00:26:47 +00:00
|
|
|
|
2017-12-28 07:10:35 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
src->image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d;
|
2017-10-04 21:27:39 +01:00
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
|
2016-11-30 00:26:47 +00:00
|
|
|
|
|
|
|
for (unsigned r = 0; r < num_rects; ++r) {
|
2017-12-28 07:10:35 +00:00
|
|
|
unsigned push_constants[6] = {
|
2016-11-30 00:26:47 +00:00
|
|
|
rects[r].src_x,
|
|
|
|
rects[r].src_y,
|
2017-12-28 07:10:35 +00:00
|
|
|
src->layer,
|
2016-11-30 00:26:47 +00:00
|
|
|
rects[r].dst_x,
|
|
|
|
rects[r].dst_y,
|
2017-12-28 07:10:35 +00:00
|
|
|
dst->layer,
|
2016-11-30 00:26:47 +00:00
|
|
|
};
|
|
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
device->meta_state.itoi.img_p_layout,
|
2017-12-28 07:10:35 +00:00
|
|
|
VK_SHADER_STAGE_COMPUTE_BIT, 0, 24,
|
2016-11-30 00:26:47 +00:00
|
|
|
push_constants);
|
|
|
|
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1);
|
|
|
|
}
|
|
|
|
}
|
2016-11-30 01:45:24 +00:00
|
|
|
|
|
|
|
static void
|
|
|
|
cleari_bind_descriptors(struct radv_cmd_buffer *cmd_buffer,
|
2017-04-13 23:26:59 +01:00
|
|
|
struct radv_image_view *dst_iview)
|
2016-11-30 01:45:24 +00:00
|
|
|
{
|
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-04-13 23:26:59 +01:00
|
|
|
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer,
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
device->meta_state.cleari.img_p_layout,
|
|
|
|
0, /* set */
|
|
|
|
1, /* descriptorWriteCount */
|
|
|
|
(VkWriteDescriptorSet[]) {
|
|
|
|
{
|
|
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 0,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]) {
|
|
|
|
{
|
|
|
|
.sampler = VK_NULL_HANDLE,
|
|
|
|
.imageView = radv_image_view_to_handle(dst_iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}
|
|
|
|
},
|
|
|
|
});
|
2016-11-30 01:45:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_meta_blit2d_surf *dst,
|
|
|
|
const VkClearColorValue *clear_color)
|
|
|
|
{
|
2017-10-04 21:27:39 +01:00
|
|
|
VkPipeline pipeline = cmd_buffer->device->meta_state.cleari.pipeline;
|
2016-11-30 01:45:24 +00:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
2017-04-13 23:26:59 +01:00
|
|
|
struct radv_image_view dst_iview;
|
2016-11-30 01:45:24 +00:00
|
|
|
|
2017-06-25 21:25:47 +01:00
|
|
|
create_iview(cmd_buffer, dst, &dst_iview);
|
2017-04-13 23:26:59 +01:00
|
|
|
cleari_bind_descriptors(cmd_buffer, &dst_iview);
|
2016-11-30 01:45:24 +00:00
|
|
|
|
2017-12-28 22:52:07 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
dst->image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pipeline = cmd_buffer->device->meta_state.cleari.pipeline_3d;
|
|
|
|
|
2017-10-04 21:27:39 +01:00
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
|
2016-11-30 01:45:24 +00:00
|
|
|
|
2017-12-28 22:52:07 +00:00
|
|
|
unsigned push_constants[5] = {
|
2016-11-30 01:45:24 +00:00
|
|
|
clear_color->uint32[0],
|
|
|
|
clear_color->uint32[1],
|
|
|
|
clear_color->uint32[2],
|
|
|
|
clear_color->uint32[3],
|
2017-12-28 22:52:07 +00:00
|
|
|
dst->layer,
|
2016-11-30 01:45:24 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
device->meta_state.cleari.img_p_layout,
|
2017-12-28 22:52:07 +00:00
|
|
|
VK_SHADER_STAGE_COMPUTE_BIT, 0, 20,
|
2016-11-30 01:45:24 +00:00
|
|
|
push_constants);
|
|
|
|
|
2017-05-02 00:49:14 +01:00
|
|
|
radv_unaligned_dispatch(cmd_buffer, dst->image->info.width, dst->image->info.height, 1);
|
2016-11-30 01:45:24 +00:00
|
|
|
}
|