2015-10-09 01:09:54 +01:00
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/*
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* Copyright © 2010 - 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#pragma once
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2015-11-17 09:37:27 +00:00
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#include <stdio.h>
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2015-10-09 01:09:54 +01:00
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#include "brw_device_info.h"
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#include "main/mtypes.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct ra_regs;
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struct nir_shader;
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struct brw_geometry_program;
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union gl_constant_value;
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struct brw_compiler {
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const struct brw_device_info *devinfo;
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struct {
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struct ra_regs *regs;
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/**
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* Array of the ra classes for the unaligned contiguous register
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* block sizes used.
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*/
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int *classes;
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/**
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* Mapping for register-allocated objects in *regs to the first
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* GRF for that object.
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*/
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uint8_t *ra_reg_to_grf;
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} vec4_reg_set;
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struct {
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struct ra_regs *regs;
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/**
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* Array of the ra classes for the unaligned contiguous register
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* block sizes used, indexed by register size.
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*/
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int classes[16];
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/**
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* Mapping from classes to ra_reg ranges. Each of the per-size
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* classes corresponds to a range of ra_reg nodes. This array stores
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* those ranges in the form of first ra_reg in each class and the
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* total number of ra_reg elements in the last array element. This
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* way the range of the i'th class is given by:
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* [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
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*/
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int class_to_ra_reg_range[17];
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/**
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* Mapping for register-allocated objects in *regs to the first
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* GRF for that object.
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*/
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uint8_t *ra_reg_to_grf;
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/**
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* ra class for the aligned pairs we use for PLN, which doesn't
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* appear in *classes.
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*/
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int aligned_pairs_class;
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} fs_reg_sets[2];
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void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
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void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
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2015-11-12 21:32:13 +00:00
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bool scalar_stage[MESA_SHADER_STAGES];
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2015-10-09 01:09:54 +01:00
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struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
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};
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/**
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* Program key structures.
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*
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* When drawing, we look for the currently bound shaders in the program
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* cache. This is essentially a hash table lookup, and these are the keys.
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*
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* Sometimes OpenGL features specified as state need to be simulated via
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* shader code, due to a mismatch between the API and the hardware. This
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* is often referred to as "non-orthagonal state" or "NOS". We store NOS
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* in the program key so it's considered when searching for a program. If
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* we haven't seen a particular combination before, we have to recompile a
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* new specialized version.
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*
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* Shader compilation should not look up state in gl_context directly, but
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* instead use the copy in the program key. This guarantees recompiles will
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* happen correctly.
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*
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* @{
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*/
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enum PACKED gen6_gather_sampler_wa {
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WA_SIGN = 1, /* whether we need to sign extend */
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WA_8BIT = 2, /* if we have an 8bit format needing wa */
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WA_16BIT = 4, /* if we have a 16bit format needing wa */
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};
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/**
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* Sampler information needed by VS, WM, and GS program cache keys.
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*/
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struct brw_sampler_prog_key_data {
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/**
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* EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
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*/
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uint16_t swizzles[MAX_SAMPLERS];
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uint32_t gl_clamp_mask[3];
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/**
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* For RG32F, gather4's channel select is broken.
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*/
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uint32_t gather_channel_quirk_mask;
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/**
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* Whether this sampler uses the compressed multisample surface layout.
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*/
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uint32_t compressed_multisample_layout_mask;
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2015-09-15 16:34:35 +01:00
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/**
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* Whether this sampler is using 16x multisampling. If so fetching from
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* this sampler will be handled with a different instruction, ld2dms_w
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* instead of ld2dms.
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*/
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uint32_t msaa_16;
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2015-10-09 01:09:54 +01:00
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/**
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* For Sandybridge, which shader w/a we need for gather quirks.
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*/
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enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
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};
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/** The program key for Vertex Shaders. */
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struct brw_vs_prog_key {
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unsigned program_string_id;
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/*
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* Per-attribute workaround flags
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*/
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uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
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bool copy_edgeflag:1;
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bool clamp_vertex_color:1;
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/**
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* How many user clipping planes are being uploaded to the vertex shader as
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* push constants.
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*
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* These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
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* clip distances.
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*/
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unsigned nr_userclip_plane_consts:4;
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/**
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* For pre-Gen6 hardware, a bitfield indicating which texture coordinates
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* are going to be replaced with point coordinates (as a consequence of a
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* call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
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* our SF thread requires exact matching between VS outputs and FS inputs,
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* these texture coordinates will need to be unconditionally included in
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* the VUE, even if they aren't written by the vertex shader.
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*/
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uint8_t point_coord_replace;
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struct brw_sampler_prog_key_data tex;
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};
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2015-11-17 09:07:39 +00:00
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/** The program key for Tessellation Control Shaders. */
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struct brw_tcs_prog_key
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{
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unsigned program_string_id;
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GLenum tes_primitive_mode;
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2015-11-26 07:35:29 +00:00
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unsigned input_vertices;
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2015-12-18 05:39:28 +00:00
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/** A bitfield of per-vertex outputs written. */
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uint64_t outputs_written;
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2015-11-17 09:07:39 +00:00
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struct brw_sampler_prog_key_data tex;
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};
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2015-11-10 22:35:27 +00:00
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/** The program key for Tessellation Evaluation Shaders. */
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struct brw_tes_prog_key
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{
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unsigned program_string_id;
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struct brw_sampler_prog_key_data tex;
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};
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2015-10-09 01:09:54 +01:00
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/** The program key for Geometry Shaders. */
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struct brw_gs_prog_key
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{
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unsigned program_string_id;
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struct brw_sampler_prog_key_data tex;
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};
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/** The program key for Fragment/Pixel Shaders. */
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struct brw_wm_prog_key {
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uint8_t iz_lookup;
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bool stats_wm:1;
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bool flat_shade:1;
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bool persample_shading:1;
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bool persample_2x:1;
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unsigned nr_color_regions:5;
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bool replicate_alpha:1;
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bool render_to_fbo:1;
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bool clamp_fragment_color:1;
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bool compute_pos_offset:1;
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bool compute_sample_id:1;
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unsigned line_aa:2;
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bool high_quality_derivatives:1;
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uint16_t drawable_height;
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uint64_t input_slots_valid;
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unsigned program_string_id;
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GLenum alpha_test_func; /* < For Gen4/5 MRT alpha test */
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float alpha_test_ref;
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struct brw_sampler_prog_key_data tex;
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};
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struct brw_cs_prog_key {
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uint32_t program_string_id;
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struct brw_sampler_prog_key_data tex;
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};
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/*
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* Image metadata structure as laid out in the shader parameter
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* buffer. Entries have to be 16B-aligned for the vec4 back-end to be
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* able to use them. That's okay because the padding and any unused
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* entries [most of them except when we're doing untyped surface
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* access] will be removed by the uniform packing pass.
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*/
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#define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
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#define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
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#define BRW_IMAGE_PARAM_SIZE_OFFSET 8
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#define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
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#define BRW_IMAGE_PARAM_TILING_OFFSET 16
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#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
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#define BRW_IMAGE_PARAM_SIZE 24
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struct brw_image_param {
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/** Surface binding table index. */
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uint32_t surface_idx;
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/** Offset applied to the X and Y surface coordinates. */
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uint32_t offset[2];
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/** Surface X, Y and Z dimensions. */
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uint32_t size[3];
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/** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
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* pixels, vertical slice stride in pixels.
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*/
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uint32_t stride[4];
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/** Log2 of the tiling modulus in the X, Y and Z dimension. */
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uint32_t tiling[3];
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/**
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* Right shift to apply for bit 6 address swizzling. Two different
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* swizzles can be specified and will be applied one after the other. The
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* resulting address will be:
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*
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* addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
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* (addr >> swizzling[1])))
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*
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* Use \c 0xff if any of the swizzles is not required.
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*/
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uint32_t swizzling[2];
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};
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struct brw_stage_prog_data {
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struct {
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/** size of our binding table. */
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uint32_t size_bytes;
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/** @{
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* surface indices for the various groups of surfaces
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*/
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uint32_t pull_constants_start;
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uint32_t texture_start;
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uint32_t gather_texture_start;
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uint32_t ubo_start;
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uint32_t ssbo_start;
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uint32_t abo_start;
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uint32_t image_start;
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uint32_t shader_time_start;
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/** @} */
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} binding_table;
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GLuint nr_params; /**< number of float params/constants */
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GLuint nr_pull_params;
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unsigned nr_image_params;
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unsigned curb_read_length;
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unsigned total_scratch;
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unsigned total_shared;
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2015-10-09 01:09:54 +01:00
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/**
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* Register where the thread expects to find input data from the URB
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* (typically uniforms, followed by vertex or fragment attributes).
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*/
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unsigned dispatch_grf_start_reg;
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bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */
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/* Pointers to tracked values (only valid once
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* _mesa_load_state_parameters has been called at runtime).
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*/
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const union gl_constant_value **param;
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const union gl_constant_value **pull_param;
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/** Image metadata passed to the shader as uniforms. */
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struct brw_image_param *image_param;
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};
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/* Data about a particular attempt to compile a program. Note that
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* there can be many of these, each in a different GL state
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* corresponding to a different brw_wm_prog_key struct, with different
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* compiled programs.
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*/
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struct brw_wm_prog_data {
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struct brw_stage_prog_data base;
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GLuint num_varying_inputs;
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GLuint dispatch_grf_start_reg_16;
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GLuint reg_blocks;
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GLuint reg_blocks_16;
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struct {
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/** @{
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* surface indices the WM-specific surfaces
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*/
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uint32_t render_target_start;
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/** @} */
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} binding_table;
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uint8_t computed_depth_mode;
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2015-10-20 22:29:39 +01:00
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bool computed_stencil;
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2015-10-09 01:09:54 +01:00
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bool early_fragment_tests;
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bool no_8;
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bool dual_src_blend;
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bool uses_pos_offset;
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bool uses_omask;
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bool uses_kill;
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|
bool pulls_bary;
|
|
|
|
uint32_t prog_offset_16;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Mask of which interpolation modes are required by the fragment shader.
|
|
|
|
* Used in hardware setup on gen6+.
|
|
|
|
*/
|
|
|
|
uint32_t barycentric_interp_modes;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Map from gl_varying_slot to the position within the FS setup data
|
|
|
|
* payload where the varying's attribute vertex deltas should be delivered.
|
|
|
|
* For varying slots that are not used by the FS, the value is -1.
|
|
|
|
*/
|
|
|
|
int urb_setup[VARYING_SLOT_MAX];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct brw_cs_prog_data {
|
|
|
|
struct brw_stage_prog_data base;
|
|
|
|
|
|
|
|
GLuint dispatch_grf_start_reg_16;
|
|
|
|
unsigned local_size[3];
|
|
|
|
unsigned simd_size;
|
|
|
|
bool uses_barrier;
|
|
|
|
bool uses_num_work_groups;
|
|
|
|
unsigned local_invocation_id_regs;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
/** @{
|
|
|
|
* surface indices the CS-specific surfaces
|
|
|
|
*/
|
|
|
|
uint32_t work_groups_start;
|
|
|
|
/** @} */
|
|
|
|
} binding_table;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Enum representing the i965-specific vertex results that don't correspond
|
|
|
|
* exactly to any element of gl_varying_slot. The values of this enum are
|
|
|
|
* assigned such that they don't conflict with gl_varying_slot.
|
|
|
|
*/
|
|
|
|
typedef enum
|
|
|
|
{
|
|
|
|
BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
|
|
|
|
BRW_VARYING_SLOT_PAD,
|
|
|
|
/**
|
|
|
|
* Technically this is not a varying but just a placeholder that
|
|
|
|
* compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
|
|
|
|
* builtin variable to be compiled correctly. see compile_sf_prog() for
|
|
|
|
* more info.
|
|
|
|
*/
|
|
|
|
BRW_VARYING_SLOT_PNTC,
|
|
|
|
BRW_VARYING_SLOT_COUNT
|
|
|
|
} brw_varying_slot;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Data structure recording the relationship between the gl_varying_slot enum
|
|
|
|
* and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
|
|
|
|
* single octaword within the VUE (128 bits).
|
|
|
|
*
|
|
|
|
* Note that each BRW register contains 256 bits (2 octawords), so when
|
|
|
|
* accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
|
|
|
|
* consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
|
|
|
|
* in a vertex shader), each register corresponds to a single VUE slot, since
|
|
|
|
* it contains data for two separate vertices.
|
|
|
|
*/
|
|
|
|
struct brw_vue_map {
|
|
|
|
/**
|
|
|
|
* Bitfield representing all varying slots that are (a) stored in this VUE
|
|
|
|
* map, and (b) actually written by the shader. Does not include any of
|
|
|
|
* the additional varying slots defined in brw_varying_slot.
|
|
|
|
*/
|
|
|
|
GLbitfield64 slots_valid;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Is this VUE map for a separate shader pipeline?
|
|
|
|
*
|
|
|
|
* Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
|
|
|
|
* without the linker having a chance to dead code eliminate unused varyings.
|
|
|
|
*
|
|
|
|
* This means that we have to use a fixed slot layout, based on the output's
|
|
|
|
* location field, rather than assigning slots in a compact contiguous block.
|
|
|
|
*/
|
|
|
|
bool separate;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
|
|
|
|
* not stored in a slot (because they are not written, or because
|
|
|
|
* additional processing is applied before storing them in the VUE), the
|
|
|
|
* value is -1.
|
|
|
|
*/
|
2015-11-10 09:17:04 +00:00
|
|
|
signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
|
2015-10-09 01:09:54 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Map from VUE slot to gl_varying_slot value. For slots that do not
|
|
|
|
* directly correspond to a gl_varying_slot, the value comes from
|
|
|
|
* brw_varying_slot.
|
|
|
|
*
|
2015-10-26 08:02:18 +00:00
|
|
|
* For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
|
2015-10-09 01:09:54 +01:00
|
|
|
*/
|
2015-11-10 09:17:04 +00:00
|
|
|
signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
|
2015-10-09 01:09:54 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Total number of VUE slots in use
|
|
|
|
*/
|
|
|
|
int num_slots;
|
2015-11-10 09:17:04 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Number of per-patch VUE slots. Only valid for tessellation control
|
|
|
|
* shader outputs and tessellation evaluation shader inputs.
|
|
|
|
*/
|
|
|
|
int num_per_patch_slots;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Number of per-vertex VUE slots. Only valid for tessellation control
|
|
|
|
* shader outputs and tessellation evaluation shader inputs.
|
|
|
|
*/
|
|
|
|
int num_per_vertex_slots;
|
2015-10-09 01:09:54 +01:00
|
|
|
};
|
|
|
|
|
2015-11-10 08:48:33 +00:00
|
|
|
void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
|
|
|
|
|
2015-10-09 01:09:54 +01:00
|
|
|
/**
|
|
|
|
* Convert a VUE slot number into a byte offset within the VUE.
|
|
|
|
*/
|
|
|
|
static inline GLuint brw_vue_slot_to_offset(GLuint slot)
|
|
|
|
{
|
|
|
|
return 16*slot;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Convert a vertex output (brw_varying_slot) into a byte offset within the
|
|
|
|
* VUE.
|
|
|
|
*/
|
2015-07-26 05:29:28 +01:00
|
|
|
static inline
|
|
|
|
GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
|
2015-10-09 01:09:54 +01:00
|
|
|
{
|
|
|
|
return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
|
|
|
|
}
|
|
|
|
|
|
|
|
void brw_compute_vue_map(const struct brw_device_info *devinfo,
|
|
|
|
struct brw_vue_map *vue_map,
|
|
|
|
GLbitfield64 slots_valid,
|
|
|
|
bool separate_shader);
|
|
|
|
|
2015-11-10 09:17:04 +00:00
|
|
|
void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
|
|
|
|
const GLbitfield64 slots_valid,
|
|
|
|
const GLbitfield is_patch);
|
|
|
|
|
2015-10-09 01:09:54 +01:00
|
|
|
enum shader_dispatch_mode {
|
|
|
|
DISPATCH_MODE_4X1_SINGLE = 0,
|
|
|
|
DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
|
|
|
|
DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
|
|
|
|
DISPATCH_MODE_SIMD8 = 3,
|
|
|
|
};
|
|
|
|
|
2015-11-12 03:24:01 +00:00
|
|
|
/**
|
|
|
|
* @defgroup Tessellator parameter enumerations.
|
|
|
|
*
|
|
|
|
* These correspond to the hardware values in 3DSTATE_TE, and are provided
|
|
|
|
* as part of the tessellation evaluation shader.
|
|
|
|
*
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
enum brw_tess_partitioning {
|
|
|
|
BRW_TESS_PARTITIONING_INTEGER = 0,
|
|
|
|
BRW_TESS_PARTITIONING_ODD_FRACTIONAL = 1,
|
|
|
|
BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum brw_tess_output_topology {
|
|
|
|
BRW_TESS_OUTPUT_TOPOLOGY_POINT = 0,
|
|
|
|
BRW_TESS_OUTPUT_TOPOLOGY_LINE = 1,
|
|
|
|
BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2,
|
|
|
|
BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum brw_tess_domain {
|
|
|
|
BRW_TESS_DOMAIN_QUAD = 0,
|
|
|
|
BRW_TESS_DOMAIN_TRI = 1,
|
|
|
|
BRW_TESS_DOMAIN_ISOLINE = 2,
|
|
|
|
};
|
|
|
|
/** @} */
|
|
|
|
|
2015-10-09 01:09:54 +01:00
|
|
|
struct brw_vue_prog_data {
|
|
|
|
struct brw_stage_prog_data base;
|
|
|
|
struct brw_vue_map vue_map;
|
|
|
|
|
2015-09-29 22:43:29 +01:00
|
|
|
/** Should the hardware deliver input VUE handles for URB pull loads? */
|
|
|
|
bool include_vue_handles;
|
|
|
|
|
2015-10-09 01:09:54 +01:00
|
|
|
GLuint urb_read_length;
|
|
|
|
GLuint total_grf;
|
|
|
|
|
|
|
|
/* Used for calculating urb partitions. In the VS, this is the size of the
|
|
|
|
* URB entry used for both input and output to the thread. In the GS, this
|
|
|
|
* is the size of the URB entry used for output.
|
|
|
|
*/
|
|
|
|
GLuint urb_entry_size;
|
|
|
|
|
|
|
|
enum shader_dispatch_mode dispatch_mode;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct brw_vs_prog_data {
|
|
|
|
struct brw_vue_prog_data base;
|
|
|
|
|
|
|
|
GLbitfield64 inputs_read;
|
|
|
|
|
|
|
|
unsigned nr_attributes;
|
|
|
|
|
|
|
|
bool uses_vertexid;
|
|
|
|
bool uses_instanceid;
|
|
|
|
};
|
|
|
|
|
2014-09-09 10:25:00 +01:00
|
|
|
struct brw_tcs_prog_data
|
|
|
|
{
|
|
|
|
struct brw_vue_prog_data base;
|
|
|
|
|
|
|
|
/** Number vertices in output patch */
|
|
|
|
int instances;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
struct brw_tes_prog_data
|
|
|
|
{
|
|
|
|
struct brw_vue_prog_data base;
|
|
|
|
|
|
|
|
enum brw_tess_partitioning partitioning;
|
|
|
|
enum brw_tess_output_topology output_topology;
|
|
|
|
enum brw_tess_domain domain;
|
|
|
|
};
|
|
|
|
|
2015-10-09 01:09:54 +01:00
|
|
|
struct brw_gs_prog_data
|
|
|
|
{
|
|
|
|
struct brw_vue_prog_data base;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Size of an output vertex, measured in HWORDS (32 bytes).
|
|
|
|
*/
|
|
|
|
unsigned output_vertex_size_hwords;
|
|
|
|
|
|
|
|
unsigned output_topology;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Size of the control data (cut bits or StreamID bits), in hwords (32
|
|
|
|
* bytes). 0 if there is no control data.
|
|
|
|
*/
|
|
|
|
unsigned control_data_header_size_hwords;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
|
|
|
|
* if the control data is StreamID bits, or
|
|
|
|
* GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
|
|
|
|
* Ignored if control_data_header_size is 0.
|
|
|
|
*/
|
|
|
|
unsigned control_data_format;
|
|
|
|
|
|
|
|
bool include_primitive_id;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* The number of vertices emitted, if constant - otherwise -1.
|
|
|
|
*/
|
|
|
|
int static_vertex_count;
|
|
|
|
|
|
|
|
int invocations;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Gen6 transform feedback enabled flag.
|
|
|
|
*/
|
|
|
|
bool gen6_xfb_enabled;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Gen6: Provoking vertex convention for odd-numbered triangles
|
|
|
|
* in tristrips.
|
|
|
|
*/
|
|
|
|
GLuint pv_first:1;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Gen6: Number of varyings that are output to transform feedback.
|
|
|
|
*/
|
|
|
|
GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Gen6: Map from the index of a transform feedback binding table entry to the
|
|
|
|
* gl_varying_slot that should be streamed out through that binding table
|
|
|
|
* entry.
|
|
|
|
*/
|
|
|
|
unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Gen6: Map from the index of a transform feedback binding table entry to the
|
|
|
|
* swizzles that should be used when streaming out data through that
|
|
|
|
* binding table entry.
|
|
|
|
*/
|
|
|
|
unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/** @} */
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Compile a vertex shader.
|
|
|
|
*
|
|
|
|
* Returns the final assembly and the program's size.
|
|
|
|
*/
|
|
|
|
const unsigned *
|
|
|
|
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
|
|
|
|
void *mem_ctx,
|
|
|
|
const struct brw_vs_prog_key *key,
|
|
|
|
struct brw_vs_prog_data *prog_data,
|
|
|
|
const struct nir_shader *shader,
|
|
|
|
gl_clip_plane *clip_planes,
|
|
|
|
bool use_legacy_snorm_formula,
|
|
|
|
int shader_time_index,
|
|
|
|
unsigned *final_assembly_size,
|
|
|
|
char **error_str);
|
|
|
|
|
2015-11-17 09:07:39 +00:00
|
|
|
/**
|
|
|
|
* Compile a tessellation control shader.
|
|
|
|
*
|
|
|
|
* Returns the final assembly and the program's size.
|
|
|
|
*/
|
|
|
|
const unsigned *
|
|
|
|
brw_compile_tcs(const struct brw_compiler *compiler,
|
|
|
|
void *log_data,
|
|
|
|
void *mem_ctx,
|
|
|
|
const struct brw_tcs_prog_key *key,
|
|
|
|
struct brw_tcs_prog_data *prog_data,
|
|
|
|
const struct nir_shader *nir,
|
|
|
|
int shader_time_index,
|
|
|
|
unsigned *final_assembly_size,
|
|
|
|
char **error_str);
|
|
|
|
|
2015-11-10 22:35:27 +00:00
|
|
|
/**
|
|
|
|
* Compile a tessellation evaluation shader.
|
|
|
|
*
|
|
|
|
* Returns the final assembly and the program's size.
|
|
|
|
*/
|
|
|
|
const unsigned *
|
|
|
|
brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
|
|
|
|
void *mem_ctx,
|
|
|
|
const struct brw_tes_prog_key *key,
|
|
|
|
struct brw_tes_prog_data *prog_data,
|
|
|
|
const struct nir_shader *shader,
|
|
|
|
struct gl_shader_program *shader_prog,
|
|
|
|
int shader_time_index,
|
|
|
|
unsigned *final_assembly_size,
|
|
|
|
char **error_str);
|
|
|
|
|
2015-10-09 01:09:54 +01:00
|
|
|
/**
|
|
|
|
* Compile a vertex shader.
|
|
|
|
*
|
|
|
|
* Returns the final assembly and the program's size.
|
|
|
|
*/
|
|
|
|
const unsigned *
|
|
|
|
brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
|
2015-10-21 00:21:09 +01:00
|
|
|
void *mem_ctx,
|
2015-10-21 20:03:21 +01:00
|
|
|
const struct brw_gs_prog_key *key,
|
2015-10-21 01:12:03 +01:00
|
|
|
struct brw_gs_prog_data *prog_data,
|
2015-10-09 01:09:54 +01:00
|
|
|
const struct nir_shader *shader,
|
|
|
|
struct gl_shader_program *shader_prog,
|
|
|
|
int shader_time_index,
|
|
|
|
unsigned *final_assembly_size,
|
|
|
|
char **error_str);
|
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|
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/**
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* Compile a fragment shader.
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*
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* Returns the final assembly and the program's size.
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*/
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const unsigned *
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brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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void *mem_ctx,
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const struct brw_wm_prog_key *key,
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struct brw_wm_prog_data *prog_data,
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const struct nir_shader *shader,
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struct gl_program *prog,
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int shader_time_index8,
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|
int shader_time_index16,
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bool use_rep_send,
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|
|
unsigned *final_assembly_size,
|
|
|
|
char **error_str);
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/**
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|
* Compile a compute shader.
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|
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*
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|
* Returns the final assembly and the program's size.
|
|
|
|
*/
|
|
|
|
const unsigned *
|
|
|
|
brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
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|
|
void *mem_ctx,
|
|
|
|
const struct brw_cs_prog_key *key,
|
|
|
|
struct brw_cs_prog_data *prog_data,
|
|
|
|
const struct nir_shader *shader,
|
|
|
|
int shader_time_index,
|
|
|
|
unsigned *final_assembly_size,
|
|
|
|
char **error_str);
|
|
|
|
|
2015-12-11 19:18:18 +00:00
|
|
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/**
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|
|
* Fill out local id payload for compute shader according to cs_prog_data.
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|
|
|
*/
|
|
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|
void
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|
|
brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
|
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|
|
void *buffer, uint32_t threads, uint32_t stride);
|
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|
|
|
2015-10-09 01:09:54 +01:00
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|
#ifdef __cplusplus
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|
|
|
} /* extern "C" */
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|
|
#endif
|